Comparator Design With VHDL [Example -1]

Very high speed integrated circuit Hardware Description Language (VHDL) is a hardware description language widely used to describe FPGA (Field Programmable Logic Gate ),IC (Integrated Circuit) and others digital or mixed signal devices.The sense of hardware description is mainly define the functionality, its behavior. So for every VHDL file there should be atleast one entity and for entity there must be atleast one architecture. Entity is system entry point for a specific device. Its describe the Hardware architecture in top level, i.e number of input / output interfaces. The device input/output roughly speaking the input/output pins are defined here with the name of port. Architecture define the hardware functionality. Like other High level programming language the VHDL give the opprtunity to block code, Functions and data types. below the example is a simple intro to design a comparator with VHDL.
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-- comparator for substration in SOBEL EDGE DETECTION block
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library ieee;
use ieee.std_logic_1164.all;

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entity global_com is


port( COMA: in std_logic_vector(20 downto 0);
OPNum: out std_logic_vector(7 downto 0)
);
end global_com;

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architecture behv of global_com is

begin

process(COMA)
begin
if (COMA<"00000010011100010000") then
OPNum <= "00000000";
else
OPNum <="11111111";
end if;
end process;

end behv;

Here the standrad library is used which is defiened by IEEE. The device has only one input and one output is defined by the Entity. Entity is a reserved keyword for VHDL and global_com is the name of the entity. COMA is the input 21 bit data Bus with standrad type (O |1). Output is 8 bit data bus .The input value is checked with predefined threshold value to defiend the output value. This functionality of this block is defined by architecture section where behv is the name of the architecture, Process can be imagine for the software devloper as a microblock of code which will run sequentially (virtual! Remember: Hardware application always run parallel this is the vital difference between software design and Hardware design. This idea will be used in simulation process through testbench ,[later] ).
I used this code while designing a FPGA to perform Sobel and prewitt Edge Detection Algorithm.
Enjoy the code ...